H9L70


PLC and LD
==========

              |    SET        RST        CR1
              |----| |--------|\|--------( )----|
              |           |                     |
              |    CR1    | RS flip-flop (1918) |
              |----| |----                      |

            ..It is important when working with electrical machines
            to mentally \"shift gears" to think in terms of LD[1].

Things we need to remember:

  0. INPUTs of the LOGICAL ELEMENT are usualy connected
     to some OUTPUTs in circuit (which are coils). That's why
     single CIRCUIT INPUT may have as much contact pairs as you want.
     It's useful to think about the finger as an "external coil".
     (see D-flip-flop example below)

           D          CLK        CR1
      |----| |--------| |--------( )
      |                     |
      |    CR1        CLK   |
      |----| |--------|/|---

  1. When drawing Ladder Diagrams we deal with CURRENT,
     When drawing Function Block Diagrams we deal with VOLTAGE.

  2. PLC-simulated and Real relay circuits may behave differently,
     because in real life all rungs are energized simultaneously,
     whereas PLC scans rungs from top (up) to bottom (down).

  3. PLC IL programming brings to us one more concept: STACK memory.
     Everything is on the stack till next OR (see also STO, LD, STR,
     "dangerous machinery")

  4. There are five STANDARD ways to program PLC:

     a) LD  -- ladder diagram, relay logic
     b) FBD -- function block diagram
     c) IL  -- instruction list
     d) ST  -- structured text
     e) SFC -- Sequential Function Chart

Digital Logic and LD
~~~~~~~~~~~~~~~~~~~~

The most important LD buiding blocks are:

  1. Normally Open contacts    ---| |---

  2. Normally Closed contacts  ---|/|---

  3. Coil                      ---( )---

On the LD-diagram block becomes unique if referred by its signature:

  LD_BLOCK_SIGNATURE = LABEL + SYMBOL

LADDER consists of rails and rungs. Unfortunately there is no logic in translation of fundamental terms to some local languages. That's why i like more the non-standard \"railway" slang:

  rail      рельса     rööbas
  rails     рельсы     rööpad, roopad

  rung      шпала      liiper
  rungs     шпалы      liiprid (kuulub koos rööbaste ja ballastiga
                       raudtee pealisehitise hulka).

Rails are drawn vertically and rungs horizontally. Left rail is energized (HIGH, HOT, VDD) while right rail is not (GND, NEUTRAL, VSS)

The most important \"Digital Logic" buiding blocks are*:

  NOT    unary operation   !
  AND    binary operation  &&
  OR     binary operation  ||
  D      D flip-flop, D data, CLK clock:
           if  D && CLK then Q=1
           if !D && CLK then Q=0

------
*) See Annex A for a longer list of \"Digital Logic" buiding blocks.

OUTPUT (Lamp, Coil)
~~~~~~~~~~~~~~~~~~~

There should be no OUTPUTs in series on single RUNG. Often LD LAMP is a COIL without contacts. Sometimes right rail (GND) is not shown, so coil have single connection wire (left). This doesn't allow us to draw two or more coils in series (Siemens). Also coil must be a rightmost element on the rung.

INPUT, Stimulus:
~~~~~~~~~~~~~~~~

Notes: Stimulus have no input. It is important to know how many inputs from other building blocks can be connected to a single output ("no limit" only on paper)

# Electronics #

Inverted stimulus. Normally OUT=1, press button to OUT=0 .

                      ^^
                     //      ___
  HOT o---/\/\/----|>|---+---o o---o GND
          R1        LED  |   PUSH
                         |
                         +--/\/\/--> OUT
                            R2

Direct stimulus, VMLab, NOT element is added

        DISPLAY        ___
  VDD o---( )----+-----o o---------o VSS
                 |
                 |   --
                 |  |  |
                 +--+  o--/\/\/----> OUT
                    |  |
                     --

# LD, Inverted stimulus #

     HOT                        GND
      |   IN1              CR1   |
      |---| |--------------(x)---|
      |                          |
      |   CR1                    |
      |---|/|-----..             |
      ..
      |   CR1                    |
      |---|/|------..            |

  INx-||-           \"normally open" push button
  CRx-()-           control relay

NOT
~~~

      CRx
   ---|/|---

  CRx -- NOT element controlleded by CRx coil

AND
~~~

      CRx      CRy
   ---| |------| |---

  CRx CRy -- AND element's inputs connected to CRx, CRy outputs.

OR
~~

         CRx
   ------| |-------
      |       |
      |  CRy  |
       --| |--

  CRx CRy -- OR element's inputs connected to CRx, CRy outputs.

D [1]
~~~~~

         D          CLK        CR1
    |----| |--------| |--------( )
    |                     |
    |    CR1        CLK   |
    |----| |--------|/|---

Annex A. Longer list of \"Digital Logic" buiding blocks
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

  Gates

    one in one out:

      NOT
      BUF

    two in one out:

      AND
      NAND
      OR
      NOR
      XOR
      XNOR
      EQ
      IF

  Combinational:

    DC   decoder, binary data to unary, example: 101 = IIIII
    CD   coder, unary data to binary, example: IIIIII = 110
    MUX  multiplexer, parallel data to serial
    DMX  demultiplexer, serial data to parallel

  Operations:

    ADD  adder, X + Y, S summa, C carry
    SUB  substractor, X - Y, D difference, B borrow
    CMP  comparator, > greater, >= greater or equal,
                     < less, <= less or equal,
                     == equal, != not equal

  Memory

    D    D flip-flop, D data, CLK clock
    RS   RS flip-flop: S set, R reset, Q normal output, !Q inversed
    JK   J jump high, K kill low, Q normal output, !Q inversed output
    T    T flip-flop: T trigger, Q normal output, !Q inversed output
    REG  Register: a line of D flip-flops with CLK
    CNT  Counter: T flip-flops in series with reset logic
    RAM  random access memory
    ROM  read only memory


Annex B. Operations Composed From The Basic Operations
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

  https://en.wikipedia.org/wiki/Boolean_algebra#Secondary_operations

    x ->  y =!x || y
    x ^^ y = ( x || y ) && !( x && y ) = and(or(x,y),nand(x,y)) # 3 gates
    x eq  y = !( x ^^ y )

The first operation, x -> y, is called material implication. If x is true then the value of x -> y is taken to be that of y. But if x is false then the value of y can be ignored; however the operation must return some truth value and there are only two choices, so the return value is the one that entails less, namely true.

The second operation, x (+) y, is called exclusive or (often abbreviated as XOR,^^ in C). It excludes the possibility of both x and y. Defined in terms of arithmetic it is addition mod 2 where 1 + 1 = 0.

The third operation, the complement of exclusive or, is equivalence or Boolean equality: x == y, is true just when x and y have the same value. Hence x (+) y as its complement can be understood as x != y, being true just when x and y are different. Equivalence counterpart in arithmetic mod 2 is x + y + 1 .


Links
~~~~~

  1. PLC: Programming Methods and Applications,
     John R. Hackworth and Frederick D. Hackworth Jr.

  2. The OpenPLC Project
     http://www.openplcproject.com/

  3. James McWhinnie, Sequential Function Charts for All
     http://www.plcdev.com/sequential_function_charts_all

  4. Node voltage method
     https://www.khanacademy.org/science/electrical-engineering
           /ee-circuit-analysis-topic/ee-dc-circuit-analysis/a
           /ee-node-voltage-method

  5. Operations Composed From The Basic Operations
     https://en.wikipedia.org/wiki/Boolean_algebra#Secondary_operations

  6. Петров И.В., Программируемые контроллеры. Стандартные языки
     и приемы прикладного проектирования, 2004
     https://www.lit62.ru/data/book/1/a2
           /1a2d26d6e6a8e8c278eb7a0057d9773b.pdf