201302041920


Level 2. Fedora18LXDE32-4GB.vdi (VirtualBox 4.26 HDD, recommended  RAM 1GB), install wine, gcc gcc-c++ kernel-devel, mount and install virtualbox guest additions, picsimulatoride692.exe (oshonsoft.com).
         

Lab 5. Stepper

  Chip:  PIC16F676
  Coils: A C B D
  PORTC: 0 2 3 1
  Pic Simulator IDE, Step Motor, Basic

      TRISC = 0
  xxx:
      PORTC = 1
      Gosub delay
      PORTC = 3
      Gosub delay
      PORTC = 2
      Gosub delay
      PORTC = 6
      Gosub delay
      PORTC = 4
      Gosub delay
      PORTC = 0xc
      Gosub delay
      PORTC = 8
      Gosub delay
      PORTC = 9
      Goto xxx
      End                                               

  delay:
      Return                                            


PIC16F84A Pin Diagram

             ---- ----
      RA2 --|    V    |-- RA1             1024 x 14b Program memory
      RA3 --|         |-- RA0               68b      Data RAM
RA4/TOCKI --|         |-- OSC1/CLKIN        64b      Data EEPROM
    !MCLR --|         |-- OSC2/CLKOUT        8 level deep hardware stack
      Vss --|         |-- Vdd               25 ma    Direct LED drive
  RB0/INT --|         |-- RB7             TMR0       8+bit timer/counter
      RB1 --|         |-- RB6
      RB2 --|         |-- RB5
      RB3 --|         |-- RB4
             ---------


  TABLE 7-2: PIC16CXXX INSTRUCTION SET   
  +--------------------------------------------------------------------------------+
  |Mnemonic     14-bit Opcode      Status  Description                   Cyc- Notes|
  |Operands     Msb           Lsb                                        les       |
  +--------------------------------------------------------------------------------+
  |BYTE-ORIENTED FILE REGISTER OPERATIONS                                          |
  |                                                                                |
  |ADDWF  f, d  00 0111 dfff ffff  CDZ     Add W and f                   1    1,2  |
  |ANDWF  f, d  00 0101 dfff ffff    Z     AND W with f                  1    1,2  |
  |CLRF   f     00 0001 lfff ffff    Z     Clear f                       1    2    |
  |CLRW         00 0001 0xxx xxxx    Z     Clear W                       1         |
  |COMF   f, d  00 1001 dfff ffff    Z     Complement f                  1    1,2  |
  |DECF   f, d  00 0011 dfff ffff    Z     Decrement f                   1    1,2  |
  |DECFSZ f, d  00 1011 dfff ffff          Decrement f, Skip if 0        1(2) 1,2,3|
  |INCF   f, d  00 1010 dfff ffff    Z     Increment f                   1    1,2  |
  |INCFSZ f, d  00 1111 dfff ffff          Increment f, Skip if 0        1(2) 1,2,3|
  |IORWF  f, d  00 0100 dfff ffff    Z     Inclusive OR W with f         1    1,2  |
  |MOVF   f, d  00 1000 dfff ffff    Z     Move f                        1    1,2  |
  |MOVWF  f     00 0000 lfff ffff          Move W to f                   1         |
  |NOP          00 0000 0xx0 0000          No Operation                  1         |
  |RLF    f, d  00 1101 dfff ffff  C       Rotate Left f through Carry   1    1,2  |
  |RRF    f, d  00 1100 dfff ffff  C       Rotate Right f through Carry  1    1,2  |
  |SUBWF  f, d  00 0010 dfff ffff  CDZ     Subtract W from f             1    1,2  |
  |SWAPF  f, d  00 1110 dfff ffff          Swap nibbles in f             1    1,2  |
  |XORWF  f, d  00 0110 dfff ffff    Z     Exclusive OR W with f         1    1,2  |
  |                                                                                |
  |BIT-ORIENTED FILE REGISTER OPERATIONS                                           |
  |                                                                                |
  |BCF    f, b  01 00bb bfff ffff          Bit Clear f                   1    1,2  |
  |BSF    f, b  01 01bb bfff ffff          Bit Set f                     1    1,2  |
  |BTFSC  f, b  01 10bb bfff ffff          Bit Test f, Skip if Clear     1(2)   3  |
  |BTFSS  f, b  01 11bb bfff ffff          Bit Test f, Skip if Set       1(2)   3  |
  |                                                                                |
  |LITERAL AND CONTROL OPERATIONS                                                  |
  |                                                                                |
  |ADDLW  k     11 111x kkkk kkkk  CDZ     Add literal and W             1         |
  |ANDLW  k     11 1001 kkkk kkkk    Z     AND literal with W            1         |
  |CALL   k     10 0kkk kkkk kkkk          Call subroutine 2                       |
  |CLRWDT       00 0000 0110 0100  !To,!Pd Clear Watchdog Timer          1         |
  |GOTO   k     10 1kkk kkkk kkkk          Go to address                 2         |
  |IORLW  k     11 1000 kkkk kkkk    Z     Inclusive OR literal with W   1         |
  |MOVLW  k     11 00xx kkkk kkkk          Move literal to W             1         |
  |RETFIE       00 0000 0000 1001          Return from interrupt         2         |
  |RETLW  k     11 01xx kkkk kkkk          Return with literal in W      2         |
  |RETURN       00 0000 0000 1000          Return from Subroutine        2         |
  |SLEEP        00 0000 0110 0011  !To!Pd  Go into standby mode          1         |
  |SUBLW  k     11 110x kkkk kkkk  CDZ     Subtract W from literal       1         |
  |XORLW  k     11 1010 kkkk kkkk    Z     Exclusive OR literal with W   1         |
  +--------------------------------------------------------------------------------+
  |Note 1: When an I/O register is modified as a function of itself                |
  |        (e.g., MOVF PORTB, 1), the value used will be that value present        |
  |        on the pins themselves. For example, if the data latch is '1'           |
  |        for a pin configured as input and is driven low by an external          |
  |        device, the data will be written back with a '0'.                       |
  |                                                                                |
  |     2: If this instruction is executed on the TMR0 register (and, where        |
  |        applicable, d = 1), the prescaler will be cleared if assigned to        |
  |        the Timer0 Module.                                                      |
  |                                                                                |
  |     3: If Program Counter (PC) is modified or a conditional test is true,      |
  |        the instruction requires two cycles. The second cycle is executed       |
  |        as a NOP.                                                               |
  +--------------------------------------------------------------------------------+
  
  TABLE 2-1: SPECIAL FUNCTION REGISTER FILE SUMMARY
  +----------------------------------------------------------------------------+
  |                                                                  Value on  |
  |Addr Name        Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on   |
  |                                                                   RESET    |
  +----------------------------------------------------------------------------+
  |Bank 0                                                                      |
  +----------------------------------------------------------------------------+
  |00h  INDF        Uses contents of FSR to address Data Memory      ---- ---- |
  |01h  TMR0        8-bit Real-Time Clock/Counter                    xxxx xxxx |
  |02h  PCL         Low Order 8 bits of the Program Counter (PC)     0000 0000 |
  |03h  STATUS (2)  IRP   RP1   RP0   !TO   !PD   Z     D     C      0001 1xxx |
  |04h  FSR         Indirect Data Memory Address Pointer 0           xxxx xxxx |
  |05h  PORTA (4)   -     -     -  RA4/T0CKI RA3  RA2  RA1    RA0    ---x xxxx |
  |06h  PORTB (5)   RB7   RB6   RB5   RB4   RB3   RB2  RB1  RB0/INT  xxxx xxxx |
  |07h  -           Unimplemented location, read as '0'              000000000 |
  |08h  EEDATA      EEPROM Data Register                             xxxx xxxx |
  |09h  EEADR       EEPROM Address Register                          xxxx xxxx |
  |0Ah  PCLATH      --- Write Buffer for upper 5 bits of the PC (1)  ---0 0000 |
  |0Bh  INTCON      GIE   EEIE  T0IE  INTE  RBIE  T0IF INTF   RBIF   0000 000x |
  +----------------------------------------------------------------------------+
  |Bank 1                                                                      |
  +----------------------------------------------------------------------------+
  |80h  INDF        Uses Contents of FSR to address Data Memory      ---- ---- |
  |81h  OPTION      RBPU  INTEDG T0CS T0SE  PSA   PS2   PS1   PS0    1111 1111 |
  |82h  PCL         Low order 8 bits of Program Counter (PC)         0000 0000 |
  |83h  STATUS (2)  IRP   RP1   RP0   TO    PD    Z     D     C      0001 1xxx |
  |84h  FSR         Indirect data memory address pointer 0           xxxx xxxx |
  |85h  TRISA       -     -     -     PORTA Data Direction Register  ---1 1111 |
  |86h  TRISB       PORTB Data Direction Register                    1111 1111 |
  |87h  -           Unimplemented location, read as '0'              0000 0000 |
  |88h  EECON1      -     -     -     EEIF  WRERR WREN  WR    RD     ---0 x000 |
  |89h  EECON2      EEPROM Control Register 2                        ---- ---- |
  |0Ah  PCLATH      --- Write buffer for upper 5 bits of the PC (1)  ---0 0000 |
  |0Bh  INTCON      GIE   EEIE  T0IE  INTE  RBIE  T0IF  INTF  RBIF   0000 000x |
  +----------------------------------------------------------------------------+
  |Legend: x = unknown, u = unchanged. - = unimplemented, read as '0',         |
  |        q = value depends on condition                                      |
  +----------------------------------------------------------------------------+
  |Note 1: The upper byte of the program counter is not directly accessible.   |
  |        PCLATH is a slave register for PC<12:8>. The contents of PCLATH can |
  |        be transferred to the upper byte of the program counter, but the    |
  |        contents of PC<12:8> are never transferred to PCLATH.               |
  |     2: The TO and PD status bits in the STATUS register are not affected by|
  |        a MCLR Reset.                                                       |
  |     3: Other (non power-up) RESETS include: external RESET through MCLR and|
  |        the Watchdog Timer Reset.                                           |
  |     4: On any device RESET, these pins are configured as inputs.           |
  |     5: This is the value that will be in the port output latch.            |
  +----------------------------------------------------------------------------+
  
  
  REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h)                    
  +--------------------------------------------------------------------+
  | bit 7                                   bit 0                      |
  +--------------------------------------------------------------------+
  | R/W-0 R/W-0 R/W-0 R-1   R-1 R/W-x R/W-x R/W-x                      |
  | IRP   RP1   RP0   !TO   !PD  Z     D     C                         |
  +--------------------------------------------------------------------+
  | Legend:                                                            |
  |                                                                    |
  | R  = Readable bit   W   = Writable bit                             |
  | U = Unimplemented bit, read as `0'                                 |
  ! n = Value at POR   '1' = Bit is set                                !
  | '0' = Bit is cleared  x  = Bit is unknown                          |
  +--------------------------------------------------------------------+
  | bit 7-6        Unimplemented: Maintain as `0'                      |
  |                                                                    |
  | bit 5     RP0: Register Bank Select bits                           |
  |                 (used for direct addressing)                       |
  |                01 = Bank 1 (80h - FFh)                             |
  |                00 = Bank 0 (00h - 7Fh)                             |
  +--------------------------------------------------------------------+
  | bit 4     TO:  Time-out bit                                        |
  |                1 =  After power-up, CLRWDT instruction,            |
  |                     or SLEEP instruction                           |
  |                0 =  A WDT time-out occurred                        |
  +--------------------------------------------------------------------+
  | bit 3     PD:  Power-down bit                                      |
  |                1 =  After power-up or by the CLRWDT instruction    |
  |                0 =  By execution of the SLEEP instruction          |
  +--------------------------------------------------------------------+
  | bit 2     Z:   Zero bit                                            |
  |                1 = The result of an arithmetic or logic operation  |
  |                    is zero                                         |
  |                0 = The result of an arithmetic or logic operation  |
  |                    is not zero                                     |
  +--------------------------------------------------------------------+
  | bit 1     D:   Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF    |
  |                instructions)                                       |
  |                (for borrow, the polarity is reversed)              |
  |                1 = A carry-out from the 4th low order bit of the   |
  |                result occurred                                     |
  |                0 = No carry-out from the 4th low order bit of the  |
  |                result                                              |
  +--------------------------------------------------------------------+
  | bit 0     C:   Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF          |
  |                instructions.  for borrow, the polarity is reversed)|
  |                1 = A carry-out from the MSB of the result occurred |
  |                0 = No carry-out from the MSB of the result occurred|
  +--------------------------------------------------------------------+
  | Note: A subtraction is executed by adding the two's complement of  |
  |       the second operand. For rotate (RRF, RLF) instructions, this |
  |       bit is loaded with either the high or low order bit of the   |
  |       source register.                                             |
  +--------------------------------------------------------------------+


Example
-------

  ---------------------------------------------
  PIC ASSEMBLER LISTING
  Line    Address Opcode  Instruction
  ---------------------------------------------
  0001    0000    1683       BSF   STATUS,RP0
  0002    0001    0186       CLRF  TRISB
  0003    0002    1283       BCF   STATUS,RP0
  0004    0003    3013       MOVLW 13h
  0005    0004    0086       MOVWF PORTB
  0006    0005    2805    A: GOTO  A
  0007    0006               END
  ---------------------------------------------
  Number of errors = 0

Hex file (produced by PicSimulatorIDE 5.83)

  :0C00000083168601831213308600052849
  :02400E00F13F80
  :00000001FF

Binary dump (produced with hex2bin)

  00000000:  83 16 86 01 83 12 13 30 - 86 00 05 28 00 00 00 00

