EASJZ


VMLAB/Spice

; AND2

;   0  0  0
;   0  1  0
;   1  0  0
;   1  1  1

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

X1    ND2  IN0  IN1   W0   ; TEST OBJECT
X2    ND2  W0   W0    OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; AND3

;   0  0  0  0    1  0  0  0
;   0  0  1  0    1  0  1  0
;   0  1  0  0    1  1  0  0
;   0  1  1  0    1  1  1  1

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

X1    ND2  IN2  IN1   W0   ; TEST OBJECT
X2    ND2  W0   W0    W1
X3    ND2  IN0  W1    W2
X4    ND2  W2   W2    OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; AND4

;   0  0  0  0  0    0  1  0  0  0    1  0  0  0  0    1  1  0  0  0
;   0  0  0  1  0    0  1  0  1  0    1  0  0  1  0    1  1  0  1  0
;   0  0  1  0  0    0  1  1  0  0    1  0  1  0  0    1  1  1  0  0
;   0  0  1  1  0    0  1  1  1  0    1  0  1  1  0    1  1  1  1  1

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

XIN4  ND2  IN3  IN3   WD4  ; latched digital stimulus on K3 with LED
D4    VDD  WD4
K3    VDD  IN3  LATCHED
R4    IN3  VSS  1K

X1    ND2  IN3  IN2   W0   ; TEST OBJECT
X2    ND2  W0   W0    W1
X3    ND2  IN1  IN9   W2
X4    ND2  W2   W2    W3
X5    ND2  W1   W3    w4
X6    ND2  W4   W4    OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; PIERCE2 (NOR2)

;   0  0  1
;   0  1  0
;   1  0  0
;   1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

X1    ND2  IN0  IN0   W0   ; TEST OBJECT
X2    ND2  IN1  IN1   W1
X3    ND2  W0   W1    W2
X3    ND2  W2   W2    OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; PIERCE3 (NOR3)

;   0  0  0  1    1  0  0  0
;   0  0  1  0    1  0  1  0
;   0  1  0  0    1  1  0  0
;   0  1  1  0    1  1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

X1    ND2  IN2  IN2   W0   ; TEST OBJECT
X2    ND2  IN1  IN1   W1
X3    ND2  W0   W1    W2
X4    ND2  W2   W2    W3
X5    ND2  IN0  IN0   W4
X6    ND2  W3   W4    W5
X7    ND2  W5   W5    OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; PIERCE4 (NOR4)

;   0  0  0  0  0    0  1  0  0  0    1  0  0  0  0    1  1  0  0  0
;   0  0  0  1  0    0  1  0  1  0    1  0  0  1  0    1  1  0  1  0
;   0  0  1  0  0    0  1  1  0  0    1  0  1  0  0    1  1  1  0  0
;   0  0  1  1  0    0  1  1  1  0    1  0  1  1  0    1  1  1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

XIN4  ND2  IN3  IN3   WD4  ; latched digital stimulus on K3 with LED
D4    VDD  WD4
K3    VDD  IN3  LATCHED
R4    IN3  VSS  1K

X1    ND2  IN3  IN3   W0   ; TEST OBJECT
X2    ND2  IN2  IN2   W1
X3    ND2  IN1  IN1   W2
X4    ND2  IN0  IN0   W3
X5    ND2  W0   W1    W4
X6    ND2  W2   W3    W5
X7    ND2  W4   W4    W6
X8    ND2  W5   W5    W7
X9    ND2  W6   W7    W8
X10   ND2  W8   W8    OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; SHEFFER2 (NAND2)

;   0  0  1
;   0  1  1
;   1  0  1
;   1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

X1    ND2  IN0  IN1   OUT  ; TEST OBJECT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; SHEFFER3 (NAND3)

;   0  0  0  1    1  0  0  1
;   0  0  1  1    1  0  1  1
;   0  1  0  1    1  1  0  1
;   0  1  1  1    1  1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

X1    ND2  IN2  IN1   W0   ; TEST OBJECT
X2    ND2  w0   w0    W1
X3    ND2  W1   IN0   OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; SHEFFER4 (NAND4)

;   0  0  0  0  1    0  1  0  0  1    1  0  0  0  1    1  1  0  0  1
;   0  0  0  1  1    0  1  0  1  1    1  0  0  1  1    1  1  0  1  1
;   0  0  1  0  1    0  1  1  0  1    1  0  1  0  1    1  1  1  0  1
;   0  0  1  1  1    0  1  1  1  1    1  0  1  1  1    1  1  1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

XIN4  ND2  IN3  IN3   WD4  ; latched digital stimulus on K3 with LED
D4    VDD  WD4
K3    VDD  IN3  LATCHED
R4    IN3  VSS  1K

X1    ND2  IN3  IN2   W0   ; TEST OBJECT
X2    ND2  IN1  IN0   W1
X3    ND2  W0   W0    W2
X4    ND2  W1   W1    W3
X5    ND2  W2   W3    OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; XOR3

;   0  0  0  0    1  0  0  1
;   0  0  1  1    1  0  1  0
;   0  1  0  1    1  1  0  0
;   0  1  1  0    1  1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

X1    ND2  IN0  IN0   W0     ; TEST OBJECT
X2    ND2  IN1  IN1   W1
X3    ND2  IN0  IN0   W3
X4    ND2  IN2  IN2   W4
X5    ND2  IN1  IN1   W5
X6    ND2  IN2  IN2   W6
X7    ND2  W0   W1    W2
X8    ND2  W3   IN1   W7
X9    ND2  W2   W2    W8
X10   ND2  W7   W7    W9
X11   ND2  W8   IN2   W10
X12   ND2  W9   W4    W11
X13   ND2  IN0  W5    W12
X14   ND2  W10  W11   W13
X15   ND2  W12  W12   W14
X16   ND2  W13  W13   W15
X17   ND2  W14  W6    W16
X18   ND2  W15  W16   OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

------------------------------------------------------------------------

; XOR4 (ZHIGALKIN4)

;   0  0  0  0  0    0  1  0  0  1    1  0  0  0  1    1  1  0  0  0
;   0  0  0  1  1    0  1  0  1  0    1  0  0  1  0    1  1  0  1  0
;   0  0  1  0  1    0  1  1  0  0    1  0  1  0  0    1  1  1  0  0
;   0  0  1  1  0    0  1  1  1  0    1  0  1  1  0    1  1  1  1  0

XIN1  ND2  IN0  IN0   WD1  ; latched digital stimulus on K0 with LED
D1    VDD  WD1
K0    VDD  IN0  LATCHED
R1    IN0  VSS  1K

XIN2  ND2  IN1  IN1   WD2  ; latched digital stimulus on K1 with LED
D2    VDD  WD2
K1    VDD  IN1  LATCHED
R2    IN1  VSS  1K

XIN3  ND2  IN2  IN2   WD3  ; latched digital stimulus on K2 with LED
D3    VDD  WD3
K2    VDD  IN2  LATCHED
R3    IN2  VSS  1K

XIN4  ND2  IN3  IN3   WD4  ; latched digital stimulus on K3 with LED
D4    VDD  WD4
K3    VDD  IN3  LATCHED
R4    IN3  VSS  1K

X1    ND2  IN3  IN3   W0   ; TEST OBJECT
X2    ND2  IN2  IN2   W1
X3    ND2  IN1  IN1   W2
X4    ND2  IN0  IN0   W3

X5    ND2  W0   W1    W4
X6    ND2  W2   IN0   W5
X7    ND2  W3   IN1   W6
X8    ND2  W0   IN2   W7
X9    ND2  W2   W3    W8
X10   ND2  IN3  W1    W9

X11   ND2  W4   W4    W10
X12   ND2  W5   W5    W11
X13   ND2  W6   W6    W12
X14   ND2  W7   W7    W13
X15   ND2  W8   W8    W14
X16   ND2  W9   W9    W15

X17   ND2  W10  W11   W16
X18   ND2  W10  W12   W17
X19   ND2  W13  W14   W18
X20   ND2  W14  W15   W19

X21   ND2  W16  W17   W20
X22   ND2  W18  W19   W21

X23   ND2  W20  W20   W22
X24   ND2  W21  W21   W23

X25   ND2  W22  W23   OUT

XOUT  ND2  OUT  OUT   WD8  ; output with LED
D8    VDD  WD8

