201301240909


Microprocessors FAQ.

Learning abstract RISC (17 instructions, sth like PIC)

Here are some fragments of AQA documentation (can be found via

  http://www.softwareforeducation.com)
  
Text is converted so, it is most suitable for autotranslation and is readable by the most online (and offline) robots available.

  
Instruction Set

  http://www.softwareforeducation.com/wikileki/index.php?title=Instruction_Set


The AQA RISC Processor

The Instruction Set is the complete list of instructions understood by the processor.

  - Traditional computer processors are complete instruction set chips (CISC) with hundreds of commands.
    
  - Microcontrollers are reduced instruction set chips (RISC). The AQA chip has only sixteen commands.
    
  - As microcontrollers have so few instructions, it does not take long to learn them all.
    
  - The commands are also very simple, along the lines of
  
    "Copy a number from box A to box B".
    "Add one to box W." 


A beginner's Example

The processor contains a register named "W", the working register. This is just a box where you can store a number.

There is a Mnemonic named ADDW. This command adds a number to the one stored in "W".

ADDW has one operand. This is the number that is going to get added to the one in "W".

If you want to add "1", the simulator expects all its numbers to be in Hexadecimal format so you have to type 0x1. 

  ADDW 0x1
  ADDW 0x2
  ADDW 0x3

  - ADDW is the mnemonic.
  
  - 0x1 is the operand.
  
  - click the "A" button to assemble the code (translate it from the human readable form into binary, understood by the processor).
  
  - click the "S" button to step through the program. You will need three clicks.
  
  - watch what happens to the "W" register. This is located near the top left of the simulator screen.
  
  - "W" contained zero, then one, then three and finally six.
  
  - if you missed any of the detail, click "A" again to reset everything and click "S" three more times. 


Flags

The processor has a Status Register (SR) containing three flags. The table above shows which flags might be set by each command.

  - C is the carry flag. This binary digit is set to one if a calculation gives a result too big to fit in eight bits.
    
  - T is the timer flag. This is set when the timer reaches zero after counting down.
    
  - Z is the zero flag. This is set when a calculation, logic operation or move leaves zero in the working register "W". 


Clock Cycles

  - Most commands take one clock cycle to finish.
  
  - The exception to this rule is commands that change the 
  
  - Program Counter register, PC.
  
  - This register keeps track of which instruction the processor is working on. 


K and (R)

  - K is usually just a number. For example in this command ...
  
    ADDW 0x1        W <= W + K
    K represents the number 0x1 

The microcontroller has 256 memory locations called the File Registers.

  - (R) in plain English is read as "the contents of file register R". 

So the command  MOVWR 0x12  means copy W into the contents of file register 0x12. 


Assembler Documentation

  http://www.softwareforeducation.com/wikileki/index.php?title=Assembler_Documentation


Contents

    1 A Microcontroller Based on the AQA Specification
    2 Instruction and Operand Fetch
    3 Power-On and Reset
    4 The Registers
        4.1 Status Register
        4.2 Timer and Prescaler Registers
    5 Configuring Input and Output Pins
    6 Memory
    7 Named Memory Locations
    8 Clock
    9 The Instruction Set
        9.1 Literals
        9.2 File Registers
        9.3 Mnemonics & Examples
    10 Define Byte - DB - Variables
    11 Reserved Words


A Microcontroller Based on the AQA Specification

  - 8 bit unidirectional address bus
  - 8 bit bidirectional data bus
  - 6 bit unidirectional instruction bus
  - R/W is a unidirectional control bus line determining read 
    or write operations
  - Clock is a unidirectional control bus line carrying the 
    clock signal used to synchronise all the microcontroller 
    operations


Instruction and Operand Fetch

  - Each instruction consists of a six bit op code and an eight
    bit operand.
    
  - The op code is fetched on the instruction bus and
    simultaneously, the operand is fetched on the data bus. 


Power-On and Reset

  - When the power is switched on, or after a reset, code 
    execution starts from address 0x00. 

This image shows the buses linking the internal microcontroller
devices.

  <== Instruction Bus (1, 6 wires)
  <== Data Bus (2, 8 wires)
  <== Address Bus (3, 8 wires)
  <== Control Bus (4, 2 wires: RW, Clock)

      +---------------------------------------+
      | Processor  (1) (2) (3) (4)            |
      |                                       |
      |  1 = Instruction Bus Register (Input) |
  1-\ |  2 = Tristate Data Bus Register (I/O) |
  2  \|  3 = Address Bus Register (Output)    |
  3  /|  4 = Control Bus Register (Output)    |
  4-/ |  W = Working Register (Accumulator)   |
      | PC = Program Counter                  |
      | SP = Stack Pointer                    |
      +---------------------------------------+
   
    
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 1 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 2 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 3 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 4 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+ R   A   M   /   R   O   M   /   F   L   A   S   H +---+
      | 5 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 6 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  1-\ +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  2  \| 7 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  3  /+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
  4-/ | 8 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | 9 |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | A |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | B |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+ REGISTER FILE containing addressable storage locations ---+
      | C |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | D |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | E |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
      | F |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+

  2-\ +-----------+    2-\ +-----------+  2-\ +-----------+
  3  \| I/0 PORTA |    3  \| I/0 PORTB |  3  \| I/0 PORTC |
  4  /|           |    4  /|           |  4  /|           |
   -/ +-----------+     -/ +-----------+   -/ +-----------+


The Registers

  - W is the working register or accumulator, through which all calculations are performed.
    
  - PC is the program counter or instruction pointer. This value (via the address bus) determines which instruction is fetched.
    
  - SP is the stack pointer used to save the return address when calling a subroutine.
    
  - The stack begins at R(0xF7) and grows towards zero. 


Status Register

  - SR is the status register containing status flags. These include:
    
    * Z (bit 2), the zero flag is set if there is a zero result in "W" after a calculation or move.
      
    * T (bit 1), the timer interrupt flag is set when the TMR register reaches zero.
      
    * C (bit 0), the carry flag is set if a calculation gives a result too big to store in 8 bits (an overflow).


Timer and Prescaler Registers

  - TMR is the timer register. This counts from any assigned number down to zero. When zero is reached, the T flag is set.
    
    * TMR is decremented after a certain number of clock pulses determined by the PRE register.
      
    * TMR is memory mapped at address R[0xFF].
          
  - PRE is the prescaler. TMR is decremented when the number of counted clock pulses matches the value in PRE. This has the effect of dividing the clock frequency by (PRE + 1).
    
    * If PRE is set to 0, TMR is disabled.
    
    * If PRE is set to 1, the clock frequency is divided by 2.
     
    * If PRE is 255, the clock frequency is divided by 256.
    
    * PRE is memory mapped at address R[0xFE]. 


Configuring Input and Output Pins

  - TRISA, TRISB, TRISC, PORTA, PORTB and PORTC are used for data input/output.
    
  - The "tris" data direction registers control tristate logic used to determine whether the port pins are inputs or outputs.
    
  - If a "tris" register bit is set to 1 then the equivalent port bit is an input.
    
  - If the "tris" bit is set to 0 then the equivalent port bit is an output.
    
  - The PORT and TRIS registers are memory mapped at addresses between R[0xF8]and R[0xFD].
    
    * 1 = I = Input
    
    * 0 = O = Output
    
    * All port pins default to Outputs because TRISA, TRISB and TRISC are initialised to Zero. 


Memory

  - R - there are 256 general purpose registers / storage locations addressed from 0 to 255 or from 0x00 to 0xFF.
        
  - The registers including and above 0xF8 are memory mapped to the I/O registers and the timer and prescaler. 


Named Memory Locations

  R(0xF8) is TRISA
  R(0xF9) is PORTA
  R(0xFA) is TRISB
  R(0xFB) is PORTB
  R(0xFC) is TRISC
  R(0xFD) is PORTC
  R(0xFE) is PRE - Prescaler
  R(0xFF) is TMR - Timer 


Clock

The simulator clock can be set between 0Hz and 120Hz. The upper limit is determined by the maximum Flash player frame rate. With older hardware, the higher clock rates might not be achieved. These slow clock speeds make visible strange effects that are never seen with real-life microcontrollers. For example, seven segment displays switching from 09 to 10 might show 19 for a brief moment because it is impossible to change both digits at the same instant. Real life processors have the same problem but they are so fast that it is rarely noticed. 


The Instruction Set

The simulator instruction set matches the AQA specification very closely. AQA did not specify the binary level details of the processor so this simulator uses binary codes which are very like those used in the Microchip family of microcontrollers.
 
  - The code is NOT case sensitive so movw is the same as MOVW and 0XFF is the same as 0xff.
    
  - Most features in the AQA specification are now available in the simulator.
    
  - Some design assumptions have been made so the exam microcontroller might differ from this one.
    

Literals

  - K is used to represent a literal, which can be
  
      * a memory location (e.g. 0x29),
      
      * a label (e.g. display:) or
      
      * a value, (e.g. 0xFA). 
      
  - KKKK KKKK represents the same as an eight bit binary number
  
  - Legal literal names begin with _ or a text character.
  
  - Literal names must not begin with a digit and must only contain _ : a-z A-Z 0-9.
  
  - Literal names must not duplicate reserved words such as MOVW or CALL.
  
  - Literal names must be unique or the assembler will not be able to resolve the ambiguity. 


File Registers

R represents a register or memory location. RR RRRR RRRR RRRR is a fourteen bit binary representation of the same.

XX XX represents a fourteen bit or four digit hexadecimal number. x (lower case) is a "don't care" value that is ignored.


Mnemonics & Examples

Differences between this simulator and the AQA version.

  - INC potentially sets both the Z and C flags. AQA only sets the Z flag.
    
  - DEC potentially sets both the Z and C flags. AQA only sets the Z flag. 
    
   Mnemonics/   Description       Operation   Hex     Flags  Clk 
   Examples                                                 
  +------------+-----------------+-----------+-------+------+---+
  |NOP         |No Operation     |None       |00 xx  |none  |1  |
  +------------+-----------------+-----------+-------+------+---+
  |CALL K      |Call procedure   |(SP)<= PC+1|20 xx  |none  |2  |
  |CALL 0x55   |at address 55h   |SP<=SP-1   |       |      |   |
  |CALL DELAY  |at label DELAY   |PC<=K      |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |RET         |Return from      |SP<=SP+1   |00 08  |none  |2  |
  |            |procedure        |PC<=(SP)   |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |INC R       |Increment the    |(R)<=(R)+1 |0A RR  |ZC    |1  |
  |INC 0x35    |contents of R    |           |       |      |   |
  |INC COUNTER |(0x35, COUNTER)  |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |DEC R       |Decrement the    |(R)<=(R)-1 |03 RR  |ZC    |1  |
  |DEC 0xCF    |contents of R    |           |       |      |   |
  |DEC TOTAL   |(0xCF, TOTAL)    |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |ADDW K      |Add K to W       |W<=W+K     |3E KK  |ZC    |1  |
  |ADDW 0x7    |Add 7 to W       |           |       |      |   |
  |ADDW TOTAL* |is legal but it  |           |       |      |   |
  |            |will add the     |           |       |      |   |
  |            |address of TOTAL |           |       |      |   |
  |            |and not the data.|           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |ANDW K      |AND K with W     |W<= W and K|39 KK  |Z     |1  |
  |ANDW 0xF0   |AND 0F           |           |       |      |   |
  |            |with W           |           |       |      |   |
  |ANDW MASK   |is legal but it  |           |       |      |   |
  |            |will AND the     |           |       |      |   |
  |            |address of MASK  |           |       |      |   |
  |            |and not the data.|           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |SUBW K      |Subtract K from W|W<=W-K     |3C KK  |ZC    |1  |
  |SUBW 0x1    |Subtract 1 from W|           |       |      |   |
  |SUBW TOTAL  |is legal but it  |           |       |      |   |
  |            |will subtract the|           |       |      |   |
  |            |address of TOTAL |           |       |      |   |
  |            |and not the data.|           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |ORW K       |OR K with W      |W<=W or K  |38 KK  |Z     |1  |
  |ORW 0x0F    |OR 01 with W     |           |       |      |   |
  |ORW MASK    |is legal but it  |           |       |      |   |
  |            |will OR the      |           |       |      |   |
  |            |address of MASK  |           |       |      |   |
  |            |and not the data.|           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |XORW K      |XOR K with W     |W<=W xor K |3A KK  |Z     |1  |
  |XORW 0xAA   |XOR AA with W    |           |       |      |   |
  |XORW MASK   |is legal but it  |           |       |      |   |
  |            |will xor the     |           |       |      |   |
  |            |address of MASK  |           |       |      |   |
  |            |and not the data.|           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |JMP K       |Jump to K (GOTO) |PC<=K      |28 KK  |      |2  |
  |JMP 0x00    |Jump to address 0|           |       |      |   |
  |JMP START   |Jump to the START|           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |JPZ K       |Jump to K if the |PC<=K      |29 KK  |if Z  |2  |
  |JPZ 0x55    |Zero Flag is set |           |       |is 1  |   |
  |JPZ FINISH  |(0x55, FINISH)   |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |JPC K       |Jump to K if the |PC<=K      |2A KK  |if C  |2  |
  |JPC 0x3C    |Carry Flag is set|           |       |is 1  |   |
  |JPC OVERFLW |(0x3C,OVERFLW)   |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |MOVWR R     |Copy from W into |(R)<=W     |01 RR  |Z     |1  |
  |MOVWR 0x50  |the register with|           |       |      |   |
  |MOVWR MY_VAR|address R        |           |       |      |   |
  |            |(0x50, MY_VAR)   |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |MOVW K      |Move K to W      |W<=K       |30 KK  |Z     |1  |
  |MOVW 0x07   |Move 0x07 into W |           |       |      |   |
  |MOVW A_LABEL|is legal but it  |           |       |      |   |
  |            |will move the    |           |       |      |   |
  |            |address of the   |           |       |      |   |
  |            |label and not the|           |       |      |   |
  |            |data.            |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |MOVRW R     |Copy the contents| W<=(R)    |08 RR  | Z    | 1 |
  |MOVRW 0x50  |of R to W        |           |       |      |   |
  |MOVRW MY_VAR|(0x50, MY_VAR)   |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
  |MOVRW SR    |Copy the contents| W<=(SR)   |09 RR  | none | 1 |
  |            |of SR into W     |           |       |      |   |
  +------------+-----------------+-----------+-------+------+---+
   <= means "is copied to"


Define Byte - DB - Variables

The AQA "Changes to Content" document describes the use of literals as both labels and values. But it does not have a way to define them in a program. Many assembler languages use DB for this purpose so it has been added as an extra to the AQA instruction set. In high level languages, these named memory locations are called variables.
 
Using DB, it is possible to name a memory location and refer to the contents of the location by name. In addition, data can be stored using DB, even if the memory location is not labelled but this is poor programing style as the program is less easy to understand.

Run this example and watch how the named memory locations get initialised when the program is assembled and how they change when it's run.

          JMP     START

  ; ===== NAMED DATA LOCATIONS =====
  DELAY:  DB      0x55    ; Address 1
  COUNT:  DB      0x10    ; Address 2
          DB      0xAA    ; Address 3

  ; ===== THE MAIN PROGRAM =====
  START:
          INC     DELAY   ; Add 1
          DEC     COUNT   ; Subtract 1
          INC     0x03    ; Poor style
          JMP     START
  ; ============================


Reserved Words

All the commands in the instruction set are reserved. In addition the following have a special meaning within the simulator and can not be used for labels.

  trisa
  porta
  trisb
  portb
  trisc
  portc
  pre
  tmr

